1. | 1 channel 5.4 Gsps 12-bit ADC |
2. | 1 channel 5.4 Gsps 12-bit DAC |
3. | One Ultra Low jitter clock synthesizer |
4. | External or internal sampling clock |
5. | External and internal sampling clock reference |
6. | External trigger input and output |
7. | User programmable Xilinx® Virtex® Ultrascale+™ VU9P/VU13P FPGA |
8. | 2x 1G64 DDR4-2666 SDRAM |
9. | 3U OpenVPX standard compliant |
10. | Air cooled and Conduction cooled rugged versions |