1. | Two 105 MSPS, 16-bit A/D channels |
2. | Two 50 MSPS, 16-bit DAC channels |
3. | +/-2V, +/-1V, +/-0.2V input ranges |
4. | +/-2V output range |
5. | 16-bits front panel DIO (8 differential pairs) |
6. | Xilinx Spartan 3A,DSP 1.8/3.4M gate FPGA |
7. | 4MB SRAM |
8. | Programmable PLL timebase |
9. | Framed, software or external triggering |
10. | Log acquisition timing and events |
11. | 44 bits digital IO on J16 |
12. | Power Management features |
13. | XMC Module (75x150 mm) |
14. | PCI Express (VITA 42.3) |
X3-25M Spartan 3 FPGA XMC module |